64-bit pipeline conditional carry adder with MTCMOS TSPC logic

In this study, a 64-bit 8-stage pipeline conditional- carry adder (CCA) with the Multi-Threshold voltage CMOS (MTCMOS) TSPC logic for power-aware applications was designed and verified. The 64-bit pipeline CCA needs 4 cycles only. Transistors on critical paths use a low threshold voltage to increase...

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Bibliographic Details
Published in2007 50th Midwest Symposium on Circuits and Systems pp. 879 - 882
Main Author Shun-Wen Cheng
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.08.2007
Subjects
64-bit
adder
Adders
Circuit simulation
CMOS logic circuits
conditional carry
conditional sum
Field programmable gate arrays
Frequency
Logic circuits
Logic design
MTCMOS
multiplexer
Multiplexing
Pipelines
Threshold voltage
TSPC
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Summary:In this study, a 64-bit 8-stage pipeline conditional- carry adder (CCA) with the Multi-Threshold voltage CMOS (MTCMOS) TSPC logic for power-aware applications was designed and verified. The 64-bit pipeline CCA needs 4 cycles only. Transistors on critical paths use a low threshold voltage to increase the operation speed. Other transistors use a normal threshold voltage to save power. Compare with single normal threshold voltage TSPC schemes, the proposed pipeline scheme has a higher operation frequency and better power-frequency ratio. Furthermore, the circuit style of proposed multiplexer can be extended on high-speed FPGA or pass-transistor logic (PTL). The simulations show that the 64-bit CCA with MTCMOS TSPC can be operated on 2.4GHz and its power / maximal frequency ratio is 43.9 muW/MHz.
ISBN:1424411750
9781424411757
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2007.4488712