A Mapping Framework for Guided Design Space Exploration of Heterogeneous MP-SoCs

When designing heterogeneous MP-SoCs designers have to take into account various objectives such as power, die size, flexibility, performance or programmability. But to be able to evaluate a given system according to these objectives, it is necessary to know how applications will behave on that syst...

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Bibliographic Details
Published in2008 Design, Automation and Test in Europe pp. 780 - 783
Main Authors Ristau, B., Limberg, T., Fettweis, G.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2008
Subjects
Analytical models
Chip scale packaging
Mobile communication
Neural networks
Optimization methods
Power system modeling
Programming profession
Refining
Space exploration
Time to market
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Summary:When designing heterogeneous MP-SoCs designers have to take into account various objectives such as power, die size, flexibility, performance or programmability. But to be able to evaluate a given system according to these objectives, it is necessary to know how applications will behave on that system. Since time-to-market is one key factor in chip design, it is important to be able to evaluate these systems at a very early design stage. Today this is usually done with simulations in languages such as Simulink or SystemC. We show how the behavior of such systems can be analyzed without the need for time-consuming implementations of simulation models. This enables fast evaluation and modification of a given system at a very early design stage allowing efficient pruning of the design space.
ISBN:3981080130
9783981080131
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2008.4484910