High throughput four-parallel RS decoder architecture for 60GHz mmWAVE WPAN systems

This paper presents a high-throughput lowcomplexity four-parallel Reed-Solomon (RS) decoder for mmWAVE WPAN systems. Four-parallel processing is used to achieve 6-Gbps data throughput and low hardware complexity. The proposed four-parallel RS decoder has been implemented 90 nm CMOS technology optimi...

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Bibliographic Details
Published in2010 Digest of Technical Papers International Conference on Consumer Electronics (ICCE) pp. 225 - 226
Main Authors Chang-Seok Choi, Hanho Lee
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2010
Subjects
Clocks
CMOS technology
Decoding
Equations
Forward error correction
Hardware
Physical layer
Polynomials
Reed-Solomon codes
Throughput
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Summary:This paper presents a high-throughput lowcomplexity four-parallel Reed-Solomon (RS) decoder for mmWAVE WPAN systems. Four-parallel processing is used to achieve 6-Gbps data throughput and low hardware complexity. The proposed four-parallel RS decoder has been implemented 90 nm CMOS technology optimized for a 1.2 V supply voltage. The implementation result shows that the proposed RS decoder can operates at a clock frequency of 400 MHz and has a data throughput 12.8-Gbps. The proposed four-parallel RS decoder architecture has high data processing rate and low hardware complexity, and also can be adapted in the FEC devices for mmWave WPAN systems with a data rate of 6-Gbps and beyond.
ISBN:9781424443147
1424443148
ISSN:2158-3994
2158-4001
DOI:10.1109/ICCE.2010.5418839