An injection-locking based programmable fractional frequency divider with 0.2 division step for quantization noise reduction

A programmable fractional frequency divider with a division step size of 0.2 has been proposed in this paper. The circuit consists of a 5-stage ring oscillator which is injection locked to an external source. The different phases from the ring oscillator are linearly combined in a Phase Combiner (PC...

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Bibliographic Details
Published in2013 Proceedings of the ESSCIRC (ESSCIRC) pp. 233 - 236
Main Authors Thirunarayanan, Raghavasimhan, Ruffieux, David, Enz, Christian
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2013
Subjects
Frequency conversion
Phase locked loops
Phase noise
Quantization (signal)
Ring oscillators
Switches
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Summary:A programmable fractional frequency divider with a division step size of 0.2 has been proposed in this paper. The circuit consists of a 5-stage ring oscillator which is injection locked to an external source. The different phases from the ring oscillator are linearly combined in a Phase Combiner (PC) based on the select signals produced by a state machine. These select signals are resynchronized with the phases to avoid glitches. This phase combined signal is then presented to a low-power dynamic divider set to division by an integer I. The result is a division by I.F where F is a multiple of the division step size 0.2. When used in a fractional-N PLL, this division step size reduction has the effect of reducing the quantization noise by 14 dB as compared to the case where a conventional multi-modulus divider (MMD) with division ratio step size of 1 is used.
ISBN:9781479906437
1479906433
ISSN:1930-8833
2643-1319
DOI:10.1109/ESSCIRC.2013.6649115