An Efficient Design-for-Testability Scheme for Motion Estimation in H.264/AVC

In this paper, a complete analysis for the input combinations of balanced and unbalanced adder trees based on C-testability conditions is presented. Based on the analysis, a simple and efficient design-for-testability scheme is proposed to implement the testable design for motion estimation (ME) cir...

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Bibliographic Details
Published in2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) pp. 1 - 4
Main Authors Tung-Hsing Wu, Yi-Lin Tsai, Soon-Jyh Chang
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2007
Subjects
Adders
Automatic voltage control
Circuit faults
Circuit simulation
Circuit synthesis
Circuit testing
Logic arrays
Logic testing
Motion estimation
Timing
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Summary:In this paper, a complete analysis for the input combinations of balanced and unbalanced adder trees based on C-testability conditions is presented. Based on the analysis, a simple and efficient design-for-testability scheme is proposed to implement the testable design for motion estimation (ME) circuit in H.264/AVC. The proposed testable scheme is applied to bit-level regular arrangement for the variable-block-size ME architecture. It guarantees 100% fault coverage with only 8 sets of test patterns. The proposed circuit design was synthesized with TSMC 0.13 mum technology. Simulation results show that the proposed design only increases about 6.5% area overhead compared to the original ME circuit with acceptable timing penalty.
ISBN:1424405823
9781424405824
DOI:10.1109/VDAT.2007.373255