Circuit Under on-chip-inductor structure (CUL) for the areal size reduction of Si-based RF circuit

A novel Circuit Under on-chip-inductor structure (CUL) including high-Q inductor (Q peak > 19) formed in the redistribution layer (RDL) is proposed to reduce the chip-size of RF embedded MCUs/SoCs. A design methodology for the CUL implementation without degrading RF performance is also discussed....

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Bibliographic Details
Published in2019 Electron Devices Technology and Manufacturing Conference (EDTM) pp. 10 - 12
Main Authors Uchida, Shinichi, Kuwajima, Teruhiro, Koh, Risho, Kuramoto, Takafumi, Ono, Akio, Kamada, Takuho, Iida, Tetsuya, Matsumoto, Akira, Nakashiba, Yasutaka
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2019
Subjects
CUL
High-Q
Inductor
Inductors
Metals
Method of moments
Phase locked loops
Phase Noise
PLL
Q-factor
Radio frequency
RDL
VCO
Voltage-controlled oscillators
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Summary:A novel Circuit Under on-chip-inductor structure (CUL) including high-Q inductor (Q peak > 19) formed in the redistribution layer (RDL) is proposed to reduce the chip-size of RF embedded MCUs/SoCs. A design methodology for the CUL implementation without degrading RF performance is also discussed. Measured phase noise of LC-VCO with proposed CUL structure suggests that a footprint can be effectively reduced without compromising performances. We estimate that PLL size can be reduced by 30% with the proposed technology.
DOI:10.1109/EDTM.2019.8731084