Improving the Performance of GALS-Based NoCs in the Presence of Process Variation

Current integration scales allow designing chip multiprocessors (CMP) where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales cause some unpredictability in manufactured devices because of process variation. In NoCs,vari...

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Published in2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip pp. 35 - 42
Main Authors Hernández, C, Roca, A, Silla, F, Flich, J, Duato, J
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2010
Subjects
Energy consumption
Frequency
Manufacturing processes
Network-on-a-chip
Planarization
Pulp manufacturing
Scalability
Semiconductor device modeling
Switches
Virtual manufacturing
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Summary:Current integration scales allow designing chip multiprocessors (CMP) where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales cause some unpredictability in manufactured devices because of process variation. In NoCs,variability may affect links and routers causing that they do not match the parameters established at design time. In this paper we first analyze the way that manufacturing deviations affect the components of a NoC by applying a comprehensive and detailed variability model to 200 instances of an 8×8 mesh NoC synthesized using 45 nm technology. A second contribution of this paper is showing that GALS-based NoCs present communication bottlenecks under process variation. To overcome this performance reduction we draft a novel approach, called performance domains, intended to reduce the negative impact of variability on application execution time. This mechanism is suitable when several applications are simultaneously running in the CMP chip.
ISBN:1424470854
9781424470853
DOI:10.1109/NOCS.2010.13