A multilevel analytical placement for 3D ICs

• Published in: 2009 Asia and South Pacific Design Automation Conference pp. 361 - 366
• Main Authors: Cong, J., Guojie Luo
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2009
• Subjects: Computer science; Delay systems; Electronic mail; Engines; Integrated circuit interconnections; Power system interconnection; Radio frequency; Temperature; Thermal force; Three-dimensional integrated circuits
• ISBN: 9781424427482; 1424427487
• ISSN: 2153-6961
• DOI: 10.1109/ASPDAC.2009.4796507

In this paper we propose a multilevel non-linear programming based 3D placement approach that minimizes a weighted sum of total wirelength and TS via number subject to area density constraints. This approach relaxes the discrete layer assignments so that they are continuous in the z-direction and the problem can be solved by an analytical global placer. A key idea is to do the overlap removal and device layer assignment simultaneously by adding a density penalty function for both area & TS via density constraints. Experimental results show that this analytical placer in a multilevel framework is effective to achieve trade-offs between wirelength and TS via number. Compared to the recently published transformation-based 3D placement method, we are able to achieve on average 12% shorter wirelength and 29% fewer TS via compared to their cases with best wirelength; we are also able to achieve on average 20% shorter wirelength and 50% fewer TS via number compared to their cases with best TS via numbers.