Data Readout Triggering for Phase 2 of the Belle II Particle Detector Experiment Based on Neural Networks

• Published in: 2018 31st IEEE International System-on-Chip Conference (SOCC) pp. 174 - 179
• Main Authors: Baehr, Steffen, Kempf, Fabian, Becker, Juergen
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2018
• Subjects: Artificial neural networks; Detectors; Field programmable gate arrays; Target tracking; Two dimensional displays; Wires
• ISSN: 2164-1706
• DOI: 10.1109/SOCC.2018.8618563

With the first collisions under way, the Belle II particle accelerator experiment is entering its second phase. This is the first time at which particle decays from collisions will be seen in the experiment's detector. Data produced by these will provide first indications whether the developed trigger and online data reduction mechanisms are working as intended. These mechanisms typically have to fulfil several hard real-time requirements, as both the throughput and maximum latency are fixed, being dictated by the experiment's parameters. One trigger mechanism that is employed in this phase is the neural z-Vertex Trigger. It uses data from the detector's drift chamber to calculate the so called z-Vertex of particle tracks that pass through the detector. This vertex is representing the position of the origin of a track along the beam line that is the z-Axis. Only if a particle originates from within the interaction point, at which the beams collide and which is defined as z = 0, they're related to the physics experiment and should be read out for further analysis. Otherwise they are to be classified as background as they are a product of unwanted effects not related to the collision. This paper presents the z-Vertex Trigger that is currently used in Phase 2 of the experiment. For that the system as well as the architecture of the neural network based architecture that was developed for use on an Virtex 6 FPGA will be presented. The developed trigger estimates the origin of a particle track within 208ns, which is well within the requirements of the experiment all while not exceeding the limited resources of the used FPGA.