A 252 × 144 SPAD Pixel Flash Lidar with 1728 Dual-Clock 48.8 PS TDCs, Integrated Histogramming and 14.9-to-1 Compression in 180NM CMOS Technology

A 252 × 144 single-photon avalanche diode (SPAD) pixel FLASH LiDAR is implemented in 180nm CMOS with 28.5μm pixel pitch and 28% fill factor. The sensor includes a collision detection bus with dynamic reallocation of 48.8 ps dual-clock time-to-digital converters (TDCs). It can operate in time-correla...

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Bibliographic Details
Published in2018 IEEE Symposium on VLSI Circuits pp. 69 - 70
Main Authors Lindner, Scott, Chao Zhang, Antolovic, Ivan Michel, Wolf, Martin, Charbon, Edoardo
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2018
Subjects
Clocks
CMOS
CMOS technology
Histogramming
Histograms
Laser radar
Latches
LiDAR
Random access memory
Robot sensing systems
SPAD
TCSPC
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DOI10.1109/VLSIC.2018.8502386

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Summary:A 252 × 144 single-photon avalanche diode (SPAD) pixel FLASH LiDAR is implemented in 180nm CMOS with 28.5μm pixel pitch and 28% fill factor. The sensor includes a collision detection bus with dynamic reallocation of 48.8 ps dual-clock time-to-digital converters (TDCs). It can operate in time-correlated single-photon counting (TCSPC), single-photon counting (SPC), peak-detection (PD) and partial-histogramming (PH) modes. The PD and PH modes are enabled by the first implementation of integrated histogramming for a full array via an SRAM based partial histogramming readout (PHR) scheme. This provides 16 5-bit bins for each pixel to enable a 14.9-to-l compression ratio.
DOI:10.1109/VLSIC.2018.8502386