Advancements on reliability-aware analog circuit design

• Published in: 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC) pp. 62 - 68
• Main Authors: Ardouin, B., Dupuy, J-Y, Godin, J., Nodjiadjim, V., Riet, M., Marc, F., Kone, G. A., Ghosh, S., Grandchamp, B., Maneux, C.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2012
• Subjects: Aging; Degradation; Integrated circuit modeling; Mathematical model; Reliability; Stress; Transistors
• ISBN: 9781467317078; 1467317071
• ISSN: 1930-8876
• DOI: 10.1109/ESSDERC.2012.6343334

This paper presents a new physics-based method for reliability prediction and modeling of Integrated Circuits (ICs). By implementing transistor degradation mechanisms via differential equations in the transistor compact model, the aging of the circuit can be simulated over (accelerated) time under real conditions. Actually, each transistor in the circuit integrates the voltage, current and temperature stress it suffers which results in (slowly) varying model parameters over time. Due to its straightforward implementation in commercial Computer Aided Design (CAD) flows, this method allows designers creating reliability-aware circuit architectures at an early stage of the design procedure, well before real circuits are actually fabricated. Application examples and results are presented for an InP/InGaAs DHBT process, but the universality of the method makes it suitable also for silicon based technologies such as CMOS and (SiGe) BiCMOS.