A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories

This paper presents a (274,256,2) DEC BCH decoder for NOR flash memories to improve the reliability. From the step-by-step algorithm, the decoding mechanism can be derived from a simple checking equation and its fully-parallel architecture is implemented to meet the low latency requirement. Moreover...

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Bibliographic Details
Published inProceedings of Technical Program of 2012 VLSI Design, Automation and Test pp. 1 - 4
Main Authors Yi-Hsun Chen, Chi-Heng Yang, Hsie-Chia Chang
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2012
Subjects
Ash
BCH codes
Composite field
Computer architecture
Decoding
Double-Error-Correcting
Hardware
Iterative decoding
NOR flash memories
Polynomials
Step-by-step decoding algorithm
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Summary:This paper presents a (274,256,2) DEC BCH decoder for NOR flash memories to improve the reliability. From the step-by-step algorithm, the decoding mechanism can be derived from a simple checking equation and its fully-parallel architecture is implemented to meet the low latency requirement. Moreover, the composite field arithmetic without extra field conversion hardware is applied to the whole decoder for further reducing complexity. By using UMC 90 nm CMOS technology, the synthesis results show that the latency is 2.5 ns with 23.2K logic gates.
ISBN:1457720809
9781457720802
DOI:10.1109/VLSI-DAT.2012.6212602