TD-SCDMA system frequency synthesizer design

This paper give a design of a TD-SCDMA frequency synthesizer using multi-ring phase-locked loop, its output frequency has the very good precision and stability.The specific circuit is simulation using 0.5 um BICMOS technology and Cadence SpectreRF. The performance of whole frequency synthesizer is:...

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Bibliographic Details
Published in2008 11th IEEE International Conference on Communication Technology pp. 275 - 277
Main Authors Wei Lin, ShiZhen Huang, Gang Tong, WeiMing Lin
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2008
Subjects
Circuit simulation
Frequency conversion
Frequency synthesizers
Phase locked loops
Phase noise
RF signals
Ring oscillators
Time division synchronous code division multiple access
Voltage control
Voltage-controlled oscillators
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Summary:This paper give a design of a TD-SCDMA frequency synthesizer using multi-ring phase-locked loop, its output frequency has the very good precision and stability.The specific circuit is simulation using 0.5 um BICMOS technology and Cadence SpectreRF. The performance of whole frequency synthesizer is: its output frequency range is 2010 MHz - 2025 MHz, the frequency changing of stride is 200 KHz, the frequency locking time is smaller than 20 us, the power voltage is 3.3 V, the power consumption is 63.26 mW.
ISBN:1424422507
9781424422500
DOI:10.1109/ICCT.2008.4716235