Timing-constrained redundant via insertion for yield optimization

According to the equivalent circuit of on-track or off-track redundant via insertion and the timing delay of each net in as the timing constraint, an enhanced timing-constrained two-phase insertion approach for yield optimization is proposed to insert on-track and off-track redundant vias. For the P...

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Bibliographic Details
Published in2007 IEEE Northeast Workshop on Circuits and Systems pp. 1126 - 1129
Main Authors Jin-Tai Yan, Bo-Yi Chiang, Zhi-Wei Chen
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.08.2007
Subjects
Benchmark testing
Computer science
Constraint optimization
Delay
Equivalent circuits
Joining processes
Maintenance engineering
Routing
Timing
Wire
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Summary:According to the equivalent circuit of on-track or off-track redundant via insertion and the timing delay of each net in as the timing constraint, an enhanced timing-constrained two-phase insertion approach for yield optimization is proposed to insert on-track and off-track redundant vias. For the Poisson yield model in redundant via insertion, the experimental results show that our proposed enhanced two-phase insertion approach only reduces 0.003%~0.005% total wire length and 0.0001%~0.0003% chip yield to maintain 100% timing constraints for the tested benchmarks.
ISBN:9781424411634
1424411637
DOI:10.1109/NEWCAS.2007.4488005