Compact modeling of LDMOS working in the third quadrant

This paper presents a method to model the drain current of LDMOS working in the 3 rd quadrant (Vds<;0), which is important for power management IC design. The DIBL effect in 3 rd quadrant is shown to be much more significant than that in 1 st quadrant (Vds>0), and is not captured by the existi...

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Bibliographic Details
Published inProceedings of the IEEE 2014 Custom Integrated Circuits Conference pp. 1 - 4
Main Authors Kejun Xia, Indana, Harihara, Gogineni, Usha
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2014
Subjects
Data models
Equations
Integrated circuit modeling
Junctions
Mathematical model
MOSFET circuits
Power MOSFET
Semiconductor device modeling
Simulation
SPICE
Threshold voltage
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Summary:This paper presents a method to model the drain current of LDMOS working in the 3 rd quadrant (Vds<;0), which is important for power management IC design. The DIBL effect in 3 rd quadrant is shown to be much more significant than that in 1 st quadrant (Vds>0), and is not captured by the existing LDMOS models. Also, the threshold voltage model is not accurate in 3 rd quadrant, where the drain-body junction is forward biased. Consequently, the existing LDMOS models underestimate the 3 rd quadrant drain current in the sub-threshold region. A drain current expression taking into account these effects for the sub-threshold region is developed and added to the device model through a SPICE component bsource. The modeling accuracy of the drain current in the 3 rd quadrant is significantly improved.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2014.6946028