Hot-carrier reliability study and simulation methodology development for 65nm technology

In this work, we report degradation study in 65 nm technology NMOS I/O transistors (Tox = 55 A¿) for different channel widths. Devices were stressed at maximum substrate current condition in order to stimulate HCI degradation. These measurements were validated using analytical equations and reliabil...

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Bibliographic Details
Published in2009 IEEE International Integrated Reliability Workshop Final Report pp. 124 - 127
Main Authors ManjulaRani, K.N., Mooraka, R.M., Patel, N., Samanta, S., Narasimhan, G., Lakshminarayanan, N., Kapre, R., Puchner, H.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2009
Subjects
Charge pumps
Circuit simulation
CMOS technology
Current measurement
Degradation
Equations
Hot carriers
Human computer interaction
Stress measurement
Threshold voltage
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Summary:In this work, we report degradation study in 65 nm technology NMOS I/O transistors (Tox = 55 A¿) for different channel widths. Devices were stressed at maximum substrate current condition in order to stimulate HCI degradation. These measurements were validated using analytical equations and reliability models extracted to be compatible with Eldo simulation tool using User Defined Reliability Model (UDRM) approach.
ISBN:9781424439218
1424439213
ISSN:1930-8841
2374-8036
DOI:10.1109/IRWS.2009.5383015