Steep subthreshold slope nanowire nanoelectromechanical field-effect transistors (NW-NEMFETs)

• Published in: 2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S) pp. 1 - 2
• Main Authors: Ji-Hun Kim, Chen, Zack C. Y., Soonshin Kwon, Jie Xiang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2013
• Subjects: Couplings; Electrodes; Electrostatics; Logic gates; Silicon; Three-dimensional displays; Transistors
• DOI: 10.1109/E3S.2013.6705882

Significant physical challenges remain for CMOS technology to decrease I off as transistor dimension and power supply voltages continue downscaling. However, a fundamental thermodynamic limit in the subthreshold slope SS = |(∂V g )/(∂lnI d )| = ln10 · k B T/q at >60 mV/dec exists at room temperature. We have designed and demonstrated the first semiconductor nanowires (NWs) and nanoelectromechanical system (NEMS) field effect transistor structure (NW-NEMFET). We have previously demonstrated 0.5 ps intrinsic delay and near ballistic operation in quantum confined semiconductor heterostructure NWFETs with diameters less than 15 nm.[1] The current design uses high performance suspended semiconductor NWs as the conduction channel, while the electrostatic pull-in of the NW towards the gate stack enables abrupt switching to the off-state leading to high frequency, low power nanoelectronics. Simulation shows that compared to planar suspended-gate FET (SGFET) design [2], NW-NEMFET allows zero SS with 10 15 on-off ratio and near 1V pull-in voltage due to enhanced 3D capacitive coupling, as well as operation at very-high-frequency (VHF) and even ultra-high-frequency (UHF) due to the NW beams high aspect ratio and small dimensions.