A low power PLL quadrature frequency synthesizer for Zigbee applications

A low power PLL quadrature frequency synthesizer for Zigbee applications is presented. The current reusing and forward-body bias techniques are applied to decrease power consumption and to improve noise characteristic of the synthesizer. The synthesizer is implemented in 0.18μm CMOS process and the...

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Bibliographic Details
Published in2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology pp. 1 - 3
Main Authors Xiaodong Liu, Wenfeng Lou, Haiyong Wang, Nanjian Wu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2012
Subjects
Frequency synthesizers
Phase locked loops
Phase noise
Power demand
Semiconductor device measurement
Synthesizers
Zigbee
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Summary:A low power PLL quadrature frequency synthesizer for Zigbee applications is presented. The current reusing and forward-body bias techniques are applied to decrease power consumption and to improve noise characteristic of the synthesizer. The synthesizer is implemented in 0.18μm CMOS process and the core chip area is about 1.2×1.2mm 2 . Measured results show that the frequency tuning range is 2.04-2.49GHz and the locking time is less than 75μs. The phase noises are -110.4dBc/Hz and -125.5dBc/Hz at the offset of 1MHz and 10MHz, respectively. The reference spur is -68.45dBc at the offset of 2.5MHz. It consumes only 3.2mA current at a 1.8V operating voltage.
ISBN:9781467324748
1467324744
DOI:10.1109/ICSICT.2012.6466716