Reliability study of 90nm CMOS inverter

• Published in: 2010 International Conference on Enabling Science and Nanotechnology (ESciNano) pp. 1 - 3
• Main Authors: Abdul Hadi, Dayanasari, Soin, N, Wan Muhamad Hatta, S F
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2010
• ISBN: 9781424488537; 1424488532
• DOI: 10.1109/ESCINANO.2010.5700968

It is well-known that the miniaturization or scaling down process of integrated circuits (ICs) has lead to the reliability issues such as Hot-Carrier (HC) and Negative Bias Temperature Instability (NBTI) effects which are very significant on p-type MOSFET. A negative voltage is applied to the gate of a pMOSFET and it attracts more holes towards the Si/SiO 2 interface. Thus the inversion holes weaken the Si-H bonds due to their lower binding energy and lead to the interface traps creation [1, 2]. Besides, this phenomenon also will re-activate the interface states. The main purpose of this paper is to study and investigate the NBTI effect on circuit level instead of the device level that has more attention from researchers nowadays. The simulation was carried out using ELDO analog simulator with reliability simulation capability. An inverter circuit with 90nm process technology had been used in this simulation. Basically, the inverter circuit was simulated at the period of T age , at which the circuit performance is to be tested.