A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS

• Published in: 2019 IEEE Custom Integrated Circuits Conference (CICC) pp. 1 - 4
• Main Authors: Pons, Marc, Muller, Christoph Thomas, Ruffieux, David, Nagel, Jean-Luc, Emery, Stephane, Burg, Andreas, Tanahashi, Shuuji, Tanaka, Yoshitaka, Takeuchi, Atsushi
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2019
• Subjects: Adaptive Body Bias; Body Bias; Frequency measurement; Ions; Low Power; Microcontroller; Microcontrollers; PVT Compensation; Random access memory; Reduced instruction set computing; SoC; Transistors; Tuning
• ISSN: 2152-3630
• DOI: 10.1109/CICC.2019.8780199

Microcontroller systems operating at low supply voltage in near- or sub-threshold regime suffer both from increased effects of PVT (Process, Voltage, Temperature) variation and from a larger share of leakage on overall power due to the reduced frequency. We show how to overcome these effects for the core and memory by exploiting the strong body factor of deeply-depleted channel CMOS at 0.5V, compensating frequency over PVT to ± 6%, achieving 30x frequency and 20x leakage scaling in a 2.56 \mu \mathrm{W} /MHz 32bit RISC Core with 3.13nW/kB 2.5 \mu \mathrm{W} /MHz SRAM. Frequency-leakage configurability in core and SRAM through adaptive body bias at fixed supply voltage is implemented using a novel automatic analog-assisted \mathrm{I}_{ON} -controlled approach.