5.7 A 256×256 40nm/90nm CMOS 3D-Stacked 120dB Dynamic-Range Reconfigurable Time-Resolved SPAD Imager

• Published in: 2019 IEEE International Solid- State Circuits Conference - (ISSCC) pp. 106 - 108
• Main Authors: Henderson, Robert K., Johnston, Nick, Hutchings, Sam W., Gyongy, Istvan, Abbas, Tarek Al, Dutton, Neale, Tyler, Max, Chan, Susan, Leach, Jonathan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2019
• Subjects: Image sensors; Laser modes; Photonics; Sensors; Timing
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC.2019.8662355

Light Detection and Ranging (LIDAR) applications pose extremely challenging dynamic range (DR) requirements on optical time-of-flight (ToF) receivers due to laser returns affected by the inverse square law over 2-3 decades of distance, diverse target reflectivity, and high solar background [1]. Integrated CMOS SPADs have a native DR exceeding 140dB, typically extending from the noise floor of few cps to 100's Mcps peak rate. To deliver this DR to downstream DSP, large SPAD time-resolved imaging arrays must count and time billions of single photon events per second demanding massively parallel on-chip pixel processing to achieve practical I/O power consumption and data rates. Hybrid Cu-Cu bonding offers a mass-manufacturable platform to implement these sensors by providing high-fill-factor SPADs optimised for NIR stacked on dense nanoscale digital processors [2]. Stacked sensor architectures involving pixel-level histogramming, on-chip peak detection and TDC/processor resource sharing are now being investigated [3-5].