A novel design methodology for error-resilient circuits in near-threshold computing

Recently, supply voltage has been reduced for low power applications, and near threshold computing (NTC) is considered as a promising solution for optimal energy efficiency. However, NTC suffers a significant performance degradation, which is prone to timing errors. Thus, in order to improve the rel...

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Bibliographic Details
Published in2016 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia) pp. 1 - 4
Main Authors Jaemin Lee, Sunmean Kim, Youngmin Kim, Seokhyeong Kang
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2016
Subjects
Conferences
Error-Resilient Circuit
Hafnium
Near-Threshold Computing (NTC)
Quine-McCluskey (Q-M) Algorithm
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Summary:Recently, supply voltage has been reduced for low power applications, and near threshold computing (NTC) is considered as a promising solution for optimal energy efficiency. However, NTC suffers a significant performance degradation, which is prone to timing errors. Thus, in order to improve the reliability of NTC operations, error-resilient techniques are indispensable, though they cause area and power overheads. In this paper, we propose a design methodology which provides an optimal implementation of error-resilient circuits. A modified Quine-McCluskey (Q-M) algorithm is exploited to earn the minimum set of error-resilient circuits without any loss of detection ability. From the proposed design flow, benchmark results show that optimal design reduces up to 72% of required flip-flops to be changed to error-resilient circuits without compromising an error detection ability.
DOI:10.1109/ICCE-Asia.2016.7804807