A low power complementary organic double-edge triggered D flip-flop with variable threshold voltage transistors

• Published in: 2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV) pp. 121 - 126
• Main Authors: Tung Xuan Pham, Huyen Thanh Pham, Toan Thanh Dao
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2017
• Subjects: Clocks; Delays; Organic thin film transistors; Threshold voltage; Time-frequency analysis
• DOI: 10.1109/ICDV.2017.8188651

Some organic double-edge triggered D flip-flops were designed with modeled organic thin-film transistors (OTFTs) and evaluated. The simulation results indicated that the circuit power consumption could be saved 20 times with the appropriate structure composing N-channel switches and TG-based MUX 2:1. In order to reduce consumption energy more deeply, the balance in the charge mobility of each transistor type needs to be set in complementary circuits. One of effective ways is varying the threshold voltage of either P-type or N-type transistors. In this work, the threshold voltage of the P-type elements have been tuned from -4.4 to 4.6 V to determine the optimal value for minimizing power dissipation of the circuit and maximizing its performance. At the optimal V th, p of -0.9 V, the circuit parameters are rise time, fall time, delay clock-to-Q and power dissipation of 57 ns, 8 ns, 52 ns, and 835 nW, respectively, at the supply voltage of 10 V and the clock pulse frequency of 1 kHz.