Modeling and Evaluation of an Energy-Efficient Hierarchical Ring Interconnect for System-on-Chip Multiprocessors

This paper describes the modeling and optimization of a hierarchical ring interconnect for system-on-chip multiprocessors. We have selected hierarchical rings for study because they exhibit properties which lend themselves to efficient SoC interconnects. Using our model, we are able to tune certain...

Full description

Saved in:
Bibliographic Details
Published in2006 IEEE North-East Workshop on Circuits and Systems pp. 201 - 204
Main Authors Bourduas, S., Kuo, B., Zilic, Z., Manjikian, N.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2006
Subjects
Clocks
Computer architecture
Delay
Design methodology
Energy consumption
Energy efficiency
Network-on-a-chip
Parallel processing
Scalability
System-on-a-chip
Online AccessGet full text

Cover

More Information
Summary:This paper describes the modeling and optimization of a hierarchical ring interconnect for system-on-chip multiprocessors. We have selected hierarchical rings for study because they exhibit properties which lend themselves to efficient SoC interconnects. Using our model, we are able to tune certain design parameters in order to reduce energy consumption. We also use dynamic clock throttling which efficiently reduces the energy consumption of the interconnect without adversely affecting system performance
ISBN:1424404169
9781424404162
DOI:10.1109/NEWCAS.2006.250914