A 14-b 32MS/s Pipelined ADC with novel fast-convergence comprehensive background calibration

This paper presents a comprehensive calibration engine for Pipelined ADCs. Linear, nonlinear, memory errors as well as errors due to the capacitor mismatch in a multi-bit DAC are all estimated and compensated for using background digital calibration techniques. The work also includes a novel approac...

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Bibliographic Details
Published in2009 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 956 - 959
Main Authors Meruva, A., Jalali-Farahani, B.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2009
Subjects
Area measurement
Calibration
Capacitors
CMOS process
Convergence
Digital filters
Engines
Error analysis
Error correction
Filtering
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ISBN1424438276
9781424438273
ISSN0271-4302
DOI10.1109/ISCAS.2009.5117916

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Summary:This paper presents a comprehensive calibration engine for Pipelined ADCs. Linear, nonlinear, memory errors as well as errors due to the capacitor mismatch in a multi-bit DAC are all estimated and compensated for using background digital calibration techniques. The work also includes a novel approach for correcting nonlinear errors that reduces the digital complexity and enhances the convergence rate of the error estimation. Conventional background calibration techniques are very slow and need millions of iterations to converge. By digitally filtering the input signal during the error estimation procedure, this work demonstrates significant improvement in convergence rate. Implemented in 0.25 um CMOS process, the pipelined ADC consumes 75 mA from 2.5 V and occupies 2.8 mm 2 of active area Measurement results show that calibration significantly improved dynamic (SNDR, SFDR) as well as static (DNL, INL) performance of the ADC.
ISBN:1424438276
9781424438273
ISSN:0271-4302
DOI:10.1109/ISCAS.2009.5117916