Optimization and Implementation of AES Algorithm Based on FPGA

• Published in: 2018 IEEE 4th International Conference on Computer and Communications (ICCC) pp. 2704 - 2709
• Main Authors: Zhang, Xiwei, Li, Meng, Hu, Jing
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2018
• Subjects: AES algorithm; Encryption; Field programmable gate arrays; FPGA; Hardware; hardware encryption; information security; Optimization; Pipelines; Registers; Throughput
• DOI: 10.1109/CompComm.2018.8780921

This paper presented an optimizing AES algorithm implementation to get smaller area and higher throughput. The main contributions of the optimization part are as follows. Initially, this paper combined multiple steps of round units into a set of more complete lookup tables to achieve parallel lookup and to obtain increased speed of the process of round units. Additionally, a dual port ROM structure was used to implement lookup tables to improve the utilization of FPGA storage units. Lastly, a fully unrolled three-stage inner and outer double pipelined architecture was used to improve data throughput. ISE software was used to carry out synthesis and timing analysis for AES algorithm module designed by this paper on Virtex-6 platform. The results showed that the area and efficiency of the AES algorithm implementation by using the optimizing design had obvious advantages over the related references. The maximum frequency and throughout of the design can be improved, which is about 470.998MHz and 60.29Gbps with small area implementation. The efficiency is increased to 26.77.