Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure

• Published in: 2008 Symposium on VLSI Technology pp. 48 - 49
• Main Authors: Kadoshima, M., Matsuki, T., Mise, N., Sato, M., Hayashi, M., Aminaka, T., Kurosawa, E., Kitajima, M., Miyazaki, S., Shiraishi, K., Chikyo, T., Yamada, K., Aoyama, T., Nara, Y., Ohji, Y.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2008
• Subjects: Electrodes; Guidelines; Logic gates; Metals; Silicon; Stress; Tin

A laminate design technology of metal gates is proposed to improve FET characteristics regardless of EOT and gate dielectric material. The laminated metal gate structures are basically composed of low-R s (sheet resistance) metal/ WF(work-function)-lowering layer/ WFM(WF determining metal). A thin W...