Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure

A laminate design technology of metal gates is proposed to improve FET characteristics regardless of EOT and gate dielectric material. The laminated metal gate structures are basically composed of low-R s (sheet resistance) metal/ WF(work-function)-lowering layer/ WFM(WF determining metal). A thin W...

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Bibliographic Details
Published in2008 Symposium on VLSI Technology pp. 48 - 49
Main Authors Kadoshima, M., Matsuki, T., Mise, N., Sato, M., Hayashi, M., Aminaka, T., Kurosawa, E., Kitajima, M., Miyazaki, S., Shiraishi, K., Chikyo, T., Yamada, K., Aoyama, T., Nara, Y., Ohji, Y.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2008
Subjects
Electrodes
Guidelines
Logic gates
Metals
Silicon
Stress
Tin
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Summary:A laminate design technology of metal gates is proposed to improve FET characteristics regardless of EOT and gate dielectric material. The laminated metal gate structures are basically composed of low-R s (sheet resistance) metal/ WF(work-function)-lowering layer/ WFM(WF determining metal). A thin WFM (~2 nm) laminated by the Si-based WF-lowering layer such as poly-Si or TaSiN brings an additional benefit of dramatic improvements in mobility and PBTI in nFETs. A thick WFM (~10 nm) suppresses the WF-lowering in pFETs. The concept of the laminate design is indispensable for improving the performance in CMOSFETs.
ISBN:142441802X
9781424418022
ISSN:0743-1562
DOI:10.1109/VLSIT.2008.4588559