Integrate LaOx-capping layer into metal gated CMOS devices using a gate-first approach for sub-45nm technology node and the device reliability thereof

This paper provides a comprehensive study on the integration of LaO x capping layer for sub-45 nm metal gated CMOS devices with Hf-based high-K dielectrics in a gate first manner. Two different integration routes, i.e. Dual Metal Dual Dielectric flow (DMDD) and Single Metal Dual Dielectric (SMDD) fl...

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Published in2008 9th International Conference on Solid-State and Integrated-Circuit Technology pp. 1260 - 1263
Main Authors HongYu Yu, Chang, S.Z., Kubicek, S., Schram, T., Wang, X.P., Biesemans, S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2008
Subjects
Annealing
CMOS technology
Electrodes
Fabrication
High-K gate dielectrics
MOCVD
MOS devices
Power lasers
Random access memory
Scalability
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Summary:This paper provides a comprehensive study on the integration of LaO x capping layer for sub-45 nm metal gated CMOS devices with Hf-based high-K dielectrics in a gate first manner. Two different integration routes, i.e. Dual Metal Dual Dielectric flow (DMDD) and Single Metal Dual Dielectric (SMDD) flow, are reported and compared. The device reliability study is also provided.
ISBN:9781424421855
1424421853
DOI:10.1109/ICSICT.2008.4734780