Fault secure FPGA-based TMR voter

Nowadays, FPGAs are used in many safety-critical applications. They are mainly subjected to Single Event Upsets (SEUs) that can flip the state of a memory cell, thereby forcing the circuit to produce an erroneous output. Fault-tolerant techniques are used to mitigate these errors. Triple Modular Red...

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Bibliographic Details
Published in2018 7th Mediterranean Conference on Embedded Computing (MECO) pp. 1 - 4
Main Authors Mahmoud, Dina G., Alkady, Gehad I., Amer, Hassanein H., Daoud, Ramez M., Adly, Ihab, Essam, Youssef, Ismail, Hassan A., Sorour, Kirollos N.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2018
Subjects
Alternating logic
Circuit faults
DPR
Fault secure
Fault tolerance
Fault tolerant systems
Fault-tolerant
Field programmable gate arrays
FPGA
SEU
Single event upsets
TMR
Transient analysis
Tunneling magnetoresistance
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Summary:Nowadays, FPGAs are used in many safety-critical applications. They are mainly subjected to Single Event Upsets (SEUs) that can flip the state of a memory cell, thereby forcing the circuit to produce an erroneous output. Fault-tolerant techniques are used to mitigate these errors. Triple Modular Redundancy (TMR) is one of the most commonly used fault-tolerant techniques in FPGAs. However, the voter is a single point of failure. This paper proposes a fault secure TMR voter design. This voter is analyzed according to its FPGA implementation. SEUs, Single Event Transients (SETs) as well as single stuck-at-0(1) faults are considered. In the presence of these faults, this voter will always produce the correct output or will give an indication of the presence of an error. Alternating Logic is utilized in the design to help with error detection while Dynamic Partial Reconfiguration (DPR) is used for error recovery.
DOI:10.1109/MECO.2018.8406016