High-density and high-speed 128Mb chain FeRAM™ with SDRAM-compatible DDR2 interface

Novel cell technologies are successfully developed for the world's highest-density and highest-speed 128 Mb chain FeRAMtrade with SDRAM-compatible 1.6 GByte/s DDR2 interface. To overcome the signal window reduction due to the capacitor shrinkage, new cell technologies such as half-pitch layout...

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Bibliographic Details
Published in2009 Symposium on VLSI Technology pp. 218 - 219
Main Authors Shimojo, Y., Konno, A., Nishimura, J., Okada, T., Yamada, Y., Kitazaki, S., Furuhashi, H., Yamazaki, S., Yahashi, K., Tomioka, K., Minami, Y., Kanaya, H., Shuto, S., Yamakawa, K., Ozaki, T., Shiga, H., Miyakawa, T., Shiratake, S., Takashima, D., Kunishima, I., Hamamoto, T., Nitayama, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2009
Subjects
128Mb
Capacitance
Capacitors
Chain and hydrogen barrier
CMOS technology
Degradation
Etching
FeRAM
Ferroelectric films
Ferroelectric materials
Hydrogen
Nonvolatile memory
Random access memory
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Summary:Novel cell technologies are successfully developed for the world's highest-density and highest-speed 128 Mb chain FeRAMtrade with SDRAM-compatible 1.6 GByte/s DDR2 interface. To overcome the signal window reduction due to the capacitor shrinkage, new cell technologies such as half-pitch layout with triangular capacitors, advanced nestled chain structure, high-density cover film and low-damage etching technique are established. New architecture with small bit line capacitance of 60 fF is also installed. With these new technologies, the cell signal window reaches 380 mV, which is sufficient for stable 128 Mb 1T1C operation.
ISBN:9781424433087
1424433088
ISSN:0743-1562