Design of a simple digital ADC using only digital blocks and delay element circuit

This paper proposes a fully Digital, Analog-to-Digital Converter (FD-ADC) which is designed by using UMC's 180 nm digital CMOS technology. The advantages of the digital ADC are its simplicity and low complexity. Power dissipation is also very less compared to other ADC architectures. The FD-ADC...

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Bibliographic Details
Published in2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) pp. 311 - 315
Main Author Senapati, Shakti Prasad
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2016
Subjects
Decoding
Delay Elements
Delays
Fully Digital CMOS Technology
Inverters
Latches
Radiation detectors
Simulation
TAD Converter
Transistors
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Summary:This paper proposes a fully Digital, Analog-to-Digital Converter (FD-ADC) which is designed by using UMC's 180 nm digital CMOS technology. The advantages of the digital ADC are its simplicity and low complexity. Power dissipation is also very less compared to other ADC architectures. The FD-ADC is suitable for low power applications and where the input signal swing is small. FD-ADC also needs very less amount of voltage supply in order to operate. The FD-ADC block uses a back-to-back voltage-to-time conversion circuit, which can be used in Time-Analog-to-Digital (TAD) converter. This TAD converter consists of a series of cascaded inverter circuits (delay elements) which increases delays in the process of conversion. The delay elements here play a vital role in the digitization of analog inputs where the input signal's amplitude variation is converted to the variation of the delay with the help of these delay elements and then the digitization of delay is carried out in order to get the final digital outputs. In this paper, the FD-ADC is having a resolution of 8-bits.
DOI:10.1109/RTEICT.2016.7807833