An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics

This paper presents an 8.69 Mvertices/s, 278 Mpixels/s, 15.7 mm 2 tiled-based 3D graphics SoC HW/SW supporting OpenGL ES 1.0 running at 139 MHz. The SoC also includes embedded circuitry to monitor run time characteristics, detect bus protocol error/inefficiency, and capture bus traces at various abs...

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Bibliographic Details
Published in2009 Asia and South Pacific Design Automation Conference pp. 131 - 132
Main Authors Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2009
Subjects
Bandwidth
Computer graphics
Consumer electronics
Costs
Debugging
Engines
Geometry
Hardware
Monitoring
Testing
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Summary:This paper presents an 8.69 Mvertices/s, 278 Mpixels/s, 15.7 mm 2 tiled-based 3D graphics SoC HW/SW supporting OpenGL ES 1.0 running at 139 MHz. The SoC also includes embedded circuitry to monitor run time characteristics, detect bus protocol error/inefficiency, and capture bus traces at various abstraction levels with compression ratio up to 98%.
ISBN:9781424427482
1424427487
ISSN:2153-6961
2153-697X
DOI:10.1109/ASPDAC.2009.4796467