Fabrication and characterization of gate-all-around silicon nanowire field effect transistors

• Published in: 2011 11th IEEE International Conference on Nanotechnology pp. 255 - 259
• Main Authors: Chan-Hoon Park, Sang-Hyun Lee, Ye-Ram Kim, Chang-Ki Baek, Yoon-Ha Jeong
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2011
• Subjects: FETs; inversion mode; Junctionless nanowire transistor; Logic gates; low frequency noise; MOSFET; Nanoscale devices; nanowire transistor; Noise; R sd; Resistance; series resistance; Silicon; Y-function
• ISBN: 9781457715143; 1457715147
• ISSN: 1944-9399; 1944-9380
• DOI: 10.1109/NANO.2011.6144669

In this paper, we show the junctionless nanowire FETs (JNTs) with gate length of 20 nm and the conventional inversion mode nanowire FETs (cINTs). The fabricated JNT has shown better electrical characteristics with high I on / I off ratio (>;10 6 ) and subthreshold slope (~75 mV/dec) than cINT, which means that the simpler fabrication process without junction formation makes the JNT a promising candidate for the next generation CMOS technology node. The nano-scale three dimensional and radial shaped structures lead to more oxide and interface traps and 1-D or 3-D configurations between the channel and source/drain. Consequently, drain current fluctuation, channel and series resistances become dominant parameters in estimating the performance of nanowire FETs (NWFETs) as the channel length is scaled down. Here, we report more reliable extraction of R sd with other device parameters such as effective mobility, threshold voltage by the Y-function method, and volume trap density by the flicker noise analysis. In addition, radius dependence of flicker noise is discussed.