3D memory with shared lithography steps: The memory industry's plan to "cram more components onto integrated circuits"

In his 1965 paper titled "cramming more components onto integrated circuits" [1], Gordon Moore predicted the number of components on a chip would increase exponentially with time due to continual reduction of feature sizes. That paradigm has continued successfully for the past 50 years, bu...

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Bibliographic Details
Published in2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) pp. 1 - 3
Main Author Sekar, Deepak C.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2014
Subjects
Flash memories
Lithography
Memory management
Microprocessors
Random access memory
Three-dimensional displays
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Summary:In his 1965 paper titled "cramming more components onto integrated circuits" [1], Gordon Moore predicted the number of components on a chip would increase exponentially with time due to continual reduction of feature sizes. That paradigm has continued successfully for the past 50 years, but cracks are starting to appear. Lithography is becoming prohibitively expensive and component quality is expected to degrade significantly beyond the 7nm node. To lower cost per bit further without relying on feature size scaling, monolithic 3D flash memories are being introduced where lithography steps are shared among multiple memory layers. In this paper, I review the flash memory industry's direction and describe 3D concepts that can scale other parts of the memory hierarchy.
ISSN:1078-621X
2577-2295
DOI:10.1109/S3S.2014.7028196