The unique challenges of debugging design and verification code jointly in SystemVerilog

The process for capturing a design and verification of that design has merged into a single language: SystemVerilog. The approach engineers take for debugging their design and verification code must also merge into a unified process. The currently available tools must mature to serve the debug needs...

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Bibliographic Details
Published inProceedings of the 2013 Forum on specification and Design Languages (FDL) pp. 1 - 7
Main Author Rich, Dave
Format Conference Proceeding
LanguageEnglish
Published European Electronic Chips & Systems design Initiative - ECSI 01.09.2013
Subjects
Debugging
Hardware
Hardware design languages
Instruction sets
Object oriented modeling
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Summary:The process for capturing a design and verification of that design has merged into a single language: SystemVerilog. The approach engineers take for debugging their design and verification code must also merge into a unified process. The currently available tools must mature to serve the debug needs of both design and verifications engineers. This paper identifies some of the different approaches and challenges created by the SystemVerilog language.
ISSN:1636-9874