Reliability analysis of copper interconnections of system-in-packaging

• Published in: 2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference pp. 52 - 55
• Main Authors: Shin-Yueh Yang, Shih-Ying Chiang, Chan-Yen Chou, Ming-Chih Yew, Kuo-Ning Chiang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2009
• Subjects: Capacitive sensors; Chip scale packaging; Copper; Integrated circuit interconnections; Integrated circuit reliability; Polymers; Thermal expansion; Thermal loading; Thermal stresses; Wafer scale integration
• ISBN: 9781424443413; 1424443415
• ISSN: 2150-5934; 2150-5942
• DOI: 10.1109/IMPACT.2009.5382307

The system-in-package (SiP) is among the popular package structures which meet the trend of integrated circuit (IC) product development. The SiP structure investigated in this study includes seven sub-chips attached to the chip carrier, with polymer applied around the chips. The polymer is used as an exceptional stress buffer layer and it can reduce the stress/strain in the solder joints. However, the shortcoming, it will affect the copper interconnection which is adversely affected by the significant stress/strain concentration under thermal loading due to the coefficient of thermal expansion (CTE) mismatch, especially at the location near the via structure. In this paper, to enhance the reliability of trace line, parametric study incorporated with the novel wafer level chip scale package (WLCSP) technology is proposed herein to reduce the stress concentration behavior both in the package-level structure and the board-level structure. The results revealed that the via on the chip side should be located away from the die edge and this can reduce the stress concentration on via caused by the expansion of the dielectric material. Furthermore, the power amplifier is the main heat source of this package. For this reason, replacing the adhesive with heat spreader would eliminate the heat spot in this package. However, building up a heat spreader in board level structure might seriously affect the reliability of via on the chip side.