A CMOS flash TDC with 0.84 - 1.3 ps resolution using standard cells

This paper proposes a new flash time-to-digital converter (TDC) design, which incorporates deterministic, variable delay into the decision elements. These are implemented with cross-coupled NAND standard cells of variable transistor widths. Both experiment and simulation are used to validate this ne...

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Bibliographic Details
Published in2012 IEEE Radio Frequency Integrated Circuits Symposium pp. 527 - 530
Main Authors Yamaguchi, T. J., Komatsu, S., Abbas, M., Asada, K., Nguyen Ngoc Mai-Khanh, Tandon, J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2012
Subjects
arbiter
Calibration
CMOS integrated circuits
Delay
deterministic variable delay
flash TDC
Logic gates
Semiconductor device measurement
slope control
Transistors
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Summary:This paper proposes a new flash time-to-digital converter (TDC) design, which incorporates deterministic, variable delay into the decision elements. These are implemented with cross-coupled NAND standard cells of variable transistor widths. Both experiment and simulation are used to validate this new design, which provides variable time-difference ranges by controlling the input slew rate. It is also possible to use the proposed flash TDC as a soft macro.
ISBN:9781467304139
1467304131
ISSN:1529-2517
2375-0995
DOI:10.1109/RFIC.2012.6242338