Controlling nanowire nucleation for integration on silicon

III-V nanowires gained general interest due to their unique properties such as high mobility, direct band gap and wide coverage of the solar spectrum. They provided advances in the fields of optoelectronics, nanoelectronics and energy applications. Recently, the focus has been shifted towards the se...

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Bibliographic Details
Published in2016 IEEE Nanotechnology Materials and Devices Conference (NMDC) pp. 1 - 2
Main Authors Dhungana, Daya S., Sartori, Nicolo, Mallet, Nicolas, Cristiano, Filadelfo, Larrieu, Guilhem, Hemeryck, Anne, Plissard, Sebastien R.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2016
Subjects
Gold
Nanoscale devices
Photonic band gap
Plasma temperature
Silicon
Substrates
Surface morphology
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Summary:III-V nanowires gained general interest due to their unique properties such as high mobility, direct band gap and wide coverage of the solar spectrum. They provided advances in the fields of optoelectronics, nanoelectronics and energy applications. Recently, the focus has been shifted towards the self-catalyzed growth of these nanowires on silicon since gold produces detrimental mid-gap states in silicon. However, the lattice mismatch and the presence of native oxide hinders the growth of vertical and uniform nanowires arrays on silicon (Si). In this context, different surface preparation methods have been developed in order to remove the native oxide present on the Si(111) substrates. Chemical treatment with HydroFluoric acid (HF), in situ H2 Plasma, and in situ high temperature annealing are considered.
DOI:10.1109/NMDC.2016.7777091