Identifying high variability speed-limiting paths under aging

Negative bias temperature instability (NBTI) is a key reliability issue in deep sub-micron technology nodes. Identifying NBTI induced high variability timing-critical paths in stipulated design cycle time is a real challenge for System-on-Chip (SoC) designers. Firstly, we identify those device param...

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Bibliographic Details
Published in2017 18th IEEE Latin American Test Symposium (LATS) pp. 1 - 6
Main Authors Srivastava, Ankush, Singh, Virendra, Singh, Adit D., Saluja, Kewal K.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2017
Subjects
Aging
Degradation
Delays
Logic gates
Negative bias temperature instability
Stress
Thermal variables control
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Summary:Negative bias temperature instability (NBTI) is a key reliability issue in deep sub-micron technology nodes. Identifying NBTI induced high variability timing-critical paths in stipulated design cycle time is a real challenge for System-on-Chip (SoC) designers. Firstly, we identify those device parameters that must be considered while performing statistical simulations to estimate maximum path delays under operational aging. By using the results of statistical simulations, this paper proposes a segment-based approach that helps in identifying high variability timing-critical paths under asymmetric aging due to NBTI. Secondly, we explore the possibility of using the proposed procedure instead of using methodologies that involve worse-case static timing analysis (STA) and time expensive Monte-Carlo (MC) simulation in identifying speed-limiting paths. Experimental results show that the path delays estimated by the proposed procedure have strong correlation with Monte-Carlo estimated path delays. At the end, we demonstrate that the proposed procedure is approx 1.4 times faster than the traditional MC simulations.
DOI:10.1109/LATW.2017.7906757