Delay defect diagnosis methodology using path delay measurements

• Published in: 2011 International Symposium on Integrated Circuits pp. 317 - 320
• Main Authors: Eun Jung Jang, Jaeyong Chung, Abraham, J. A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2011
• Subjects: Circuit faults; Delay; Integrated circuit modeling; Silicon; Very large scale integration
• ISBN: 161284863X; 9781612848631
• ISSN: 2325-0631
• DOI: 10.1109/ISICir.2011.6131960

With aggressive device scaling, timing failures have become more prevalent due to manufacturing defects and process variations. When timing failure occurs, it is important to take corrective actions immediately. Therefore, an efficient and fast diagnosis method is essential. In this paper, we propose a new diagnostic method using timing information. Our method approximately estimates all the segment delays of measured paths in a design using inequality-constrained least squares methods. Then, the proposed method ranks the possible locations of delay defects based on the difference between estimated segment delays and the expected values of segment delays. The method works well for multiple delay defects as well as single delay defects. Experiment results show that our method yields good diagnostic resolution. With the proposed method, the average first hit rank (FHR), was within 7 for single delay defect and within 8 for multiple delay defects.