A 0.2V 16Kb 9T SRAM with bitline leakage equalization and CAM-assisted write performance boosting for improving energy efficiency

An energy efficient 9T SRAM with bitline leakage equalization and Content-Addressable-Memory-assisted (CAM-assisted) performance boosting techniques is presented. The equalized read bitline leakage improves the read bitline swing by 6.8× at 0.2V. The proposed CAM-assisted boosting technique enhances...

Full description

Saved in:
Bibliographic Details
Published in2012 IEEE Asian Solid State Circuits Conference (A-SSCC) pp. 73 - 76
Main Authors Bo Wang, Truc Quynh Nguyen, Anh Tuan Do, Jun Zhou, Minkyu Je, Kim, Tony T.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2012
Online AccessGet full text

Cover

More Information
Summary:An energy efficient 9T SRAM with bitline leakage equalization and Content-Addressable-Memory-assisted (CAM-assisted) performance boosting techniques is presented. The equalized read bitline leakage improves the read bitline swing by 6.8× at 0.2V. The proposed CAM-assisted boosting technique enhances the write performance of the multi-threshold CMOS (MTCMOS) SRAM array implemented with higher-Vth (HVT) devices. The inserted tiny CAM conceals the slow data development after data flipping, and therefore improves overall operating frequency in the near threshold region. A 16Kb SRAM test chip was fabricated in 65nm CMOS technology and showed the minimum energy of 0.33 pJ at 0.4V.
DOI:10.1109/IPEC.2012.6522630