A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package

An in-package interconnect for in-package memory application in InFO package has been demonstrated. Technology: TSMC 16FF + InFO. 89.6GByte/s total bandwidth is achieved with 256-DQ operating in 2.8Gbit/s and 0.3V-swing. Low power: IO (0.062pJ/bit); PHY (0.424pJ/bit). Low latency: Write (4.75T+1.5T=...

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Bibliographic Details
Published in2016 IEEE Hot Chips 28 Symposium (HCS) pp. 1 - 32
Main Authors Mu-Shan Lin, Chien-Chun Tsai, Cheng-Hsiang Hsieh, Wen-Hung Huang, Yu-Chi Chen, Shu-Chun Yang, Chin-Ming Fu, Hao-Jie Zhan, Jinn-Yeh Chien, Shao-Yu Li, Chen, Y.-H, Kuo, C.-C, Shih-Peng Tai, Yamada, Kazuyoshi
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.08.2016
Subjects
Bandwidth
Companies
High performance computing
Integrated circuit interconnections
Manufacturing
Random access memory
Security
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Summary:An in-package interconnect for in-package memory application in InFO package has been demonstrated. Technology: TSMC 16FF + InFO. 89.6GByte/s total bandwidth is achieved with 256-DQ operating in 2.8Gbit/s and 0.3V-swing. Low power: IO (0.062pJ/bit); PHY (0.424pJ/bit). Low latency: Write (4.75T+1.5T=6.25T); Read (2+1.875=3.875T). 0.3V signal integrity on the un-probed IO has been clarified. 420ps (0.84UI) Eye width; 225mV (75%) Eye height. Prompt and automatic timing-calibration scheme.
DOI:10.1109/HOTCHIPS.2016.7936211