Improvement in Electrical Properties of A1/La2O3/ZrO2/ Gate Stack Deposited on LaON Passivated GaAs Substrate

• Published in: 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) pp. 1 - 4
• Main Authors: Barhate, Viral N., Agrawal, Khushabu S., Patil, Vilas S., Mahajan, Ashok M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2020
• Subjects: bilayer high-k; Capacitance-voltage characteristics; CET; Dielectric constant; Gallium arsenide; High-k dielectric materials; interface trap density; LaON interfacial layer; Logic gates; Manufacturing; MOS capacitors; PEALD
• DOI: 10.1109/EDTM47692.2020.9117895

The PEALD deposited La 2 O 3 /ZrO2 bilayer high-k on with and without LaON passivated GaAs substrates were investigated. The structural and electrical properties of bilayered MOS capacitors were studied in detailed. The dielectric constant (k) of =\mathbf{20.75} , effective oxide charge (\mathbf{Q}_{\mathbf{eff}}) of \mathbf{1.094}\times \mathbf{10}^{\mathbf{12}}\mathbf{cm}^{-\mathbf{2}} , interface trapped density (\mathbf{D}_{\mathbf{it}})\mathbf{1.655}\times \mathbf{10}^{\mathbf{12}}\mathbf{eV}^{-\mathbf{1}}\mathbf{cm}^{-\mathbf{2}} and leakage current density (\mathbf{J}=\mathbf{8.93}\times \mathbf{10}^{-\mathbf{5}}\ \mathbf{at\ \ 1V}) were obtained for the LaON passivated GaAs MOS capacitor. The lowest capacitance equivalent thickness (CET) of 0.649 nm extracted from C-V curve for LaON passivated GaAs sample. The presence of LaON passivation layer in MOS device effectively blocks the formation of As-oxides and Ga-oxides at interface, which significantly improves the interfacial and electrical properties of the device and can be the effective passivation for the futuristic high mobility substrate devices