A novel 700V deep trench isolated double RESURF LDMOS with P-sink layer

• Published in: 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) pp. 323 - 326
• Main Authors: Shikang Cheng, Dong Fang, Ming Qiao, Sen Zhang, Guangsheng Zhang, Yan Gu, Yitao He, Xin Zhou, Zhao Qi, Zhaoji Li, Bo Zhang
• Format: Conference Proceeding
• Language: English
• Published: IEEJ 01.05.2017
• Subjects: 700V; Deep Trench Isolation; LDMOS; P-sink Layer; silicon limit
• ISBN: 488686094X; 9784886860941
• ISSN: 1946-0201
• DOI: 10.23919/ISPSD.2017.7988954

A novel DTI double RESURF LDMOS with P-sink layer is presented and experimentally demonstrated in this paper. The novel structure features a P-sink layer around the bottom of deep trench, which is formed with the Deep N-type Well (DNW) after the process of high temperature driving in. The highly doped P-sink layer restrains the extension of depletion region along the horizontal direction, improving the isolation performance. According to the simulation results, the surface electric field peak of the proposed DTI LDMOS is reduced by 35 % due to the enhanced depletion effect of P-sink layer. Meanwhile, the concentration of DNW and P-top region are increased, thus the R on, sp is decreased. Furthermore, the isolation region area is reduced significantly so that the chip size will be minimized. The LDMOS with R on, sp of 96.2 mΩ·cm 2 and BV of 758 V is experimentally achieved, which breaks the conventional R on, sp -BV silicon limit of double RESURF technology.