High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs

• Published in: 2014 24th International Conference on Field Programmable Logic and Applications (FPL) pp. 1 - 4
• Main Authors: Ahmed, Rehan, Bsoul, Assem A. M., Wilton, Steven J. E., Hallschmid, Peter, Klukas, Richard
• Format: Conference Proceeding
• Language: English
• Published: Technical University of Munich (TUM) 01.09.2014
• Subjects: Acceleration; Benchmark testing; Computer architecture; Design automation; Fabrics; Field programmable gate arrays; FPGA; Hardware; High-level Synthesis; Run-time/Dynamic Power Gating; Static Leakage Power
• ISSN: 1946-147X; 1946-1488
• DOI: 10.1109/FPL.2014.6927433

Static leakage power consumption is critical in modern FPGAs for many applications. Dynamic Power-Gating (DPG), in which parts of the FPGA in-use logic blocks are powered-down at run-time, is a promising technique to reduce the static power. Adoption of such emerging DPG enabled FPGA architectures remains challenging as the current tool-chains to program the FPGA does not support this type of power-gating. Moreover, manually identifying profitable power-gating opportunities in an application requires significant design expertise and is time consuming. In this paper, we propose a high-level synthesis-based design framework that exploits the dynamic power-gating feature of the FPGAs to minimize the static power dissipation. We use this framework on a set of CHStone benchmark suite and demonstrate that power-gating opportunities for hardware accelerators can be identified in an automatic way. Results show that up to 96% reduction in static energy is achieved for individual accelerators using dynamic power-gating technique.