Design and DfT of a High-Speed Area-Efficient Embedded Asynchronous FIFO

Embedded first-in first-out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded ripple-through FIFO module with asynchronous read and write clocks. The implementation is based on a micropipeline architecture and is at least a factor two smaller than S...

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Bibliographic Details
Published in2007 Design, Automation & Test in Europe Conference & Exhibition pp. 1 - 6
Main Authors Wielage, P., Marinissen, E.J., Altheimer, M., Wouters, C.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2007
Subjects
Automatic testing
Clocks
Communication system control
Design for testability
Integrated circuit testing
Marine technology
Network-on-a-chip
Pipelines
Random access memory
Software libraries
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Summary:Embedded first-in first-out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded ripple-through FIFO module with asynchronous read and write clocks. The implementation is based on a micropipeline architecture and is at least a factor two smaller than SRAM-based and standard-cell-based counterparts. This paper gives an overview of the most important design features of the new FIFO module and describes its test and design-for-test approach
ISBN:3981080122
9783981080124
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2007.364399