3-D modeling of fringing gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs

In this paper, an analytical model for fringing gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs (SNWTs) is proposed. The fringing gate capacitances of the SNWT are divided into three parts: sidewall capacitance C side ; parallel capacitance C gsd ; perpendicular capacitance...

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Bibliographic Details
Published in2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) pp. 256 - 259
Main Authors TaeYoon An, SoYoung Kim
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2013
Subjects
Analytical models
Capacitance
Conformal mapping
Logic gates
Mercury (metals)
Solid modeling
Wires
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Summary:In this paper, an analytical model for fringing gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs (SNWTs) is proposed. The fringing gate capacitances of the SNWT are divided into three parts: sidewall capacitance C side ; parallel capacitance C gsd ; perpendicular capacitance C gex . Each capacitance is calculated using the following methods: conformal mapping, integral and non-dimensionalization. The proposed model is verified with a three-dimensional field solver, Raphael. Based on the proposed model, the fringing capacitance can be easily predicted in the vertically and horizontally stacked multi-wire SNWTs.
ISBN:9781467357333
1467357332
ISSN:1946-1569
1946-1577
DOI:10.1109/SISPAD.2013.6650623