3-D modeling of fringing gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs
In this paper, an analytical model for fringing gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs (SNWTs) is proposed. The fringing gate capacitances of the SNWT are divided into three parts: sidewall capacitance C side ; parallel capacitance C gsd ; perpendicular capacitance...
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Published in | 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) pp. 256 - 259 |
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Main Authors | , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.09.2013
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Subjects | |
Online Access | Get full text |
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Summary: | In this paper, an analytical model for fringing gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs (SNWTs) is proposed. The fringing gate capacitances of the SNWT are divided into three parts: sidewall capacitance C side ; parallel capacitance C gsd ; perpendicular capacitance C gex . Each capacitance is calculated using the following methods: conformal mapping, integral and non-dimensionalization. The proposed model is verified with a three-dimensional field solver, Raphael. Based on the proposed model, the fringing capacitance can be easily predicted in the vertically and horizontally stacked multi-wire SNWTs. |
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ISBN: | 9781467357333 1467357332 |
ISSN: | 1946-1569 1946-1577 |
DOI: | 10.1109/SISPAD.2013.6650623 |