Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology

Fully-integrated 40-Gb/s pulse pattern generator (PPG) and bit-error-rate tester (BERT) chipsets has been presented in 65-nm CMOS technology. Using external clock inputs, the PPG and BERT achieve full operation with ultra-wide data range from 40 Mb/s to 40 Gb/s. Built-in PLL and CDR circuits are als...

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Bibliographic Details
Published in2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) pp. 109 - 112
Main Authors Guan-Sing Chen, Chin-Yang Wu, Chen-Lun Lin, Hao-Wei Hung, Jri Lee
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2014
Subjects
Bit error rate
Boosting
Clocks
CMOS integrated circuits
Gain
Jitter
Temperature sensors
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Summary:Fully-integrated 40-Gb/s pulse pattern generator (PPG) and bit-error-rate tester (BERT) chipsets has been presented in 65-nm CMOS technology. Using external clock inputs, the PPG and BERT achieve full operation with ultra-wide data range from 40 Mb/s to 40 Gb/s. Built-in PLL and CDR circuits are also included to provide robustness for standard specification testing.
ISBN:1479940909
9781479940905
DOI:10.1109/ASSCC.2014.7008872