Fabrication technique for arrays of Germanium-on-Nothing nanowires

• Published in: 2009 International Semiconductor Device Research Symposium pp. 1 - 2
• Main Authors: Thomas, P.M., Pawlik, D.J., Romanczyk, B., Freeman, E., Rommel, S.L., Kurinec, S.K., Cheng, Z., Li, J., Park, J.S., Hydrick, J.M., Fiorenza, J.G., Lochtefeld, A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2009
• Subjects: Chemicals; Contamination; Etching; Fabrication; FETs; Light emitting diodes; Nanowires; Production; Semiconductor materials; Substrates
• ISBN: 1424460301; 9781424460304
• DOI: 10.1109/ISDRS.2009.5378043

The authors have presented a CMOS compatible method for the production and incorporation of NW arrays that may be a basis for future NWFETs and other NW based devices. This work also hints to the possibility of incorporating NWs of different semiconductor material onto the same substrate to achieve high performance FETs, LEDs, and other devices. The authors surmise that alternating layers of Ge and Si could produce stacked Ge NWs similar to the Si NW stacks in other work. Finally, the use of chemicals readily available to most fabrication facilities as well as the use of TMAH, to avoid the mobile ion contamination that can plaque other Si etchants, provides for a series of steps that could be incorporated into a CMOS facility.